The Network on Chip (NoC) architecture was introduced in [Dal01] as a better alternative to global wiring structures, used to interconnect different Intellectual Property (IP) blocks. The NoC in [Dal01] has a regular tile-based architecture that offers several advantages over traditional interconnection networks. The structured network wiring allows for a better control of the electrical parameters of the network’s wires. This provides the opportunity to obtain reduced power consumption. Another advantage of NoCs is given by modularity and standard network interfaces, which provide re-usability and interoperability of the modules. Wiring resources are shared by the communicating IPs: when one module is not communicating, other modules can still use the wiring resources used by the (now) idle module. No global wiring is used by a Network on Chip. The IPs communicate by sending packets to one another. In order to exploit a Network on Chip, the design flow of a NoC architecture needs the following steps [Hu03]:
- divide the application into a graph of concurrent tasks;
- assign and schedule the application tasks to the available IPs;
- map each IP to a NoC tile, such that the metrics of interest are optimized.
The mapping problem for NoCs [Mar09] was addressed first in [Hu03], where it was formulated as the topological placement of the IPs onto the on-chip tiles. This is an NP-hard problem because the search space increases factorially with the system size. For example, a NoC with 8×8 tiles theoretically allows 64! mappings.
I am proposing UniMap, a Unified Framework for the evaluation and optimization of existing application mapping algorithms for NoCs. The main benefits of this framework are:
- the comparison of algorithms on the same NoC design;
- the evaluation of application mapping algorithms’ performance, on different NoC architectures (e.g.: since such algorithms are mainly evaluated on 2D mesh NoCs, other topologies may also be tested);
- the potential optimization of an algorithm on a particular NoC;
- the possibility of identifying which is the most suitable application mapping algorithm for a specific NoC design.
ABPS is my only research project as an undergraduate student. Thanks to Assoc. Prof. Dr. Adrian Florea, the project started as a small lab project (a trace-driven simulator for the Simple Perceptron branch predictor) and has soon become a larger project which also involved the work done by Horia Calborean and Adrian Crapciu. We managed to build a trace-driven branch prediction simulator. Professor Florea suggested the name ABPS (from Advanced Branch Prediction Simulator), which seemed appropiate since our simulator allows testing several two-level and perceptron based brach prediction schemes. The simulator is trace-driven and contains three benchmark suites, but other benchmarks can be easily integrated. ABPS also addresses the open problem of unbiased branches (you may find papers about unbiased branches on the webpage of Prof. Dr. Lucian Vinţan). I think that ABPS is the first tool in the world which allows the investigation of unbiased branches.
Thanks to Adrian Florea and Lucian Vinţan, we have published a paper about ABPS, at EUROSIM 2007 (see my Publications page if you are interested in the paper).
You may find more details on the project’s page: http://abps.sourceforge.net/
The work on this project was suspended in October 2007 because we had to work on our BSc Thesis (which involved something else) and now (since November 2008), Horia Calborean and myself have become PhD students in the field of multicores & parallel programming. Therefore, if you are interested in further developing ABPS, do not hesitate to contact me.